Technical Field
Embodiments described herein are related to circuits and methods for operating integrated circuits in subthreshold voltage regions.
Description of the Related Art
The increasing popularity of mobile devices continues to drive the trend toward low power designs. Mobile devices are often operated on a limited energy supply such as a battery, as opposed to the essentially unlimited energy supply of a wall plug. To provide long battery life, low power consumption in the device is key.
Voltage scaling is one mechanism for lowering power consumption/energy use in an integrated circuit. Because power consumption increases with the square of the supply voltage magnitude, reductions in supply voltage magnitude provide quadratic reductions in power consumption. In the past, the limit to voltage scaling has been based on the threshold voltage of the transistors in the design. Generally, the threshold voltage is the gate-to-source voltage that is necessary to reach saturation current in the transistor. Below the threshold voltage, current varies significantly with variation in the gate-to-source voltage. Above the threshold voltage, the current can still vary with gate-to-source voltage but the variation is much smaller. Operating in the saturation region simplifies the timing analysis of the design.
More recently, scaling the supply voltage magnitude near the threshold voltage or even below the threshold voltage has been investigated. Operation in this region is challenging to traditional circuit designs. For example, if the threshold voltage of a transistor is 200 mV+/−50 mV and the supply voltage is 600 mV, the excess of the supply voltage over the threshold voltage (“headroom”) is between 350-450 mV, or a variation of about +/−10%. In the saturation region, a variation of 10% in the gate to source voltage generally has a minor effect on circuit delay. If the supply voltage is to be 300 mV, the headroom is between 50-150 mV, or +/−50%. Such a variation can cause more significant timing problems. If the supply voltage is reduced into the subthreshold voltage region, variations in current are much more pronounced even for small variations in the threshold voltage, dramatically impacting delays in the circuit.
Traditionally, operation near or in the threshold voltage region has been accomplished by redesigning the circuit library available to the designer and/or logic synthesis tools, to limit the number of transistors in a “stack” (e.g. the N-type metal-oxide-semiconductor (NMOS) transistors in a traditional NAND gate) and using alternative circuit designs for gates in the library. The process of limiting and changing the library is referred to as pruning Once the library is pruned, the integrated circuit design must be resynthesized and retimed. Pruning, resynthesis, and retiming all take additional effort and time and may cause additional problems within the integrated circuit.